The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device and, more particularly, to a semiconductor device in which the short channel effect of a MOS transistor is suppressed and a method of manufacturing the semiconductor device.
Recently, in the important potions of computers or communication equipments, large-scale integrated circuits (LSI) each constituted in such a manner that a large number of transistors, resistors, etc. are connected together so as to constitute an electric circuit and thus integrated on one chip are used in many cases.
Due to this, the performance of an equipment as a whole is deeply connected to the performance of the LSI itself. The enhancement in performance of the LSI itself can be realized by minute-structuring the elements. For example, in case of a MOS transistor, by reducing the size thereof, the increase in speed thereof, the reduction in power consumption thereof, and the enhancement in the degree of integration thereof could so far be realized.
However, various problems are caused as a result of the reduction in size of the elements. For example, the shortening of the channel length achieves the effect of lowering the channel resistance on the one hand but, on the other, gives rise to the problem that a short-channel effect is brought about.
As for the suppression of this short-channel effect, it is already found that it is effective to reduce the junction depth of the source/drain; particularly in case of a low supply voltage, it is effective to form a shallow diffusion layer with a high impurity atom concentration at a position near the gate electrode. In other word, it is effective to replace, in the LDD structure, its shallow diffused layer with a low impurity atom concentration with a diffused layer with a high impurity atom concentration. This diffused layer with a high impurity atom concentration is ordinarily known as an extension layer. Or, by enhancing the impurity atom concentration in the region immediately beneath the channel region (by forming a punch through prevention layer), the effect of suppressing the punch through phenomenon is obtained.
However, in case of any of the above-mentioned methods, there is encountered the difficulty that, as the element size is reduced (as the degree of structural minuteness of the elements is furthered), the formation of a very sharp profile, that is, the formation of a very shallow extension layer with a high impurity atom concentration, the formation of a punch through prevention layer beneath a very shallow channel region, etc. become harder.
Further, as a result of the reduction in size of the elements, the ratios of the various parasitic components become relatively high. For example, the junction capacitance of the source/drain is brought to so high a ratio as to affect the operating speed.
As a countermeasure to the above-mentioned difficulty, there has been tried the method of removing the junction capacitance in such a manner that, using a very thin SOI (Silicon On Insulator) substrate, the bottom surface of the junction is contacted with the buried oxide film.
However, in case of this method, the price of the SOI substrate is high and thus costs high, and besides, since the element operation region lies on the buried oxide film, the carries produced through the element operation are accumulated. That is, a so-called substrate accumulation effect is caused, and thus, there arises the problem that it becomes difficult to operate the elements stably.
Further, there has also been proposed the technical concept that a back gate is formed in the buried oxide film in a very thin SOI substrate, and, to this back gate, a voltage is applied to render the region beneath the channel into a depleted state and thus to prevent a punch through, whereby the short channel effect can be suppressed.
As described above, in order to suppress the short channel effect of the MOS transistor, the introduction of an extension layer or a punch through prevention layer has been proposed, but there arises the other problem that, as the structural minuteness of the elements is furthered, it becomes hard to suppress the short channel effect of the MOS transistor.
The present invention has been made by taking the above-mentioned circumstances into consideration, and it is the object of the invention to provide a semiconductor device in which the short channel effect of the field-effect transistor can be effectively suppressed in spite of furthering the structural minuteness of the elements and also to provide a method of manufacturing the semiconductor device mentioned above.
In order to achieve the above-mentioned object, the semiconductor device according to the present invention comprises a semiconductor substrate, a field-effect transistor formed in a region of the semiconductor substrate wherein the semiconductor substrate has a cavity beneath the region in which the field-effect transistor is formed.
Here, it is pointed out that the inner surface of the cavity should desirably covered with an insulation film. Further, a semiconductor region which is composed of a semiconductor substance different from the semiconductor substance constituting the semiconductor substrate and functions to suppress the spread of the depletion layer beneath the region in which the field-effect transistor forming region is formed may alternatively be formed in place of the above-mentioned cavity.
Further, another semiconductor device according to the present invention comprises a semiconductor substrate, a lateral field-effect transistor formed in a flat portion of the semiconductor substrate, and an insulator formed in the semiconductor substrate beneath the region in which the field-effect transistor is formed.
Here, the cavity, the semiconductor layer or the insulator should desirably be formed in the semiconductor substrate beneath the channel region of the field-effect transistor.
Further, the cavity, the semiconductor layer or the insulator should desirably be formed in the semiconductor substrate beneath the source region and the drain region of the field-effect transistor.
Further, the cavity, the semiconductor layer or the insulator should desirably be formed in the silicon substrate beneath the channel region, the source region and the drain region.
Further, the field-effect transistor is, for example, a MOS transistor or a MESFET.
Further, in case of the cavity or the semiconductor layer, the field-effect transistor may be formed either in a flat portion or in a projected portion of the substrate surface.
Another semiconductor device according to the present invention comprises a field-effect transistor formed in a semiconductor substrate, an electrode formed in the semiconductor substrate beneath the region in which the field-effect transistor is formed, and an insulated gate structure comprised of this electrode and an insulation film formed in the interface between the electrode and the semiconductor substrate.
A method of manufacturing a semiconductor device according to the present invention comprises the steps of forming a groove in the surface of a semiconductor substrate, closing the open portion of the groove by performing a heat treatment under reduced pressure to thereby form a cavity, and forming a field-effect transistor on the region including the cavity.
Here, the above-mentioned heat treatment under reduced pressure should desirably be carried out in a deoxidizing atmosphere. The deoxidizing atmosphere is, for example, a hydrogen atmosphere.
The method of manufacturing a semiconductor device according to the present invention comprises the step of forming a groove in the surface of a semiconductor substrate, the step of filling the interior of the groove to an intermediate depth thereof with an insulator, the step of filling up the remaining portion of the groove with a semiconductor, and the step of forming a lateral field-effect transistor on a region including the insulator.
In the semiconductor device according to the present invention, the spread of the depletion layers from the source and the drain stops at the location where the cavity, the semiconductor layer or the insulator lies, so that the spread of the depletion layer in the channel region can be prevented. Therefore, according to the present invention, even if the structural minuteness of the device is furthered, the short channel effect of the field-effect transistor can be effectively suppressed.
Further, in case the cavity, the semiconductor layer or the insulator is formed in the semiconductor substrate beneath the source region and the drain region of the field-effect transistor, the junction capacitance of the source/drain can be sufficiently reduced without bringing about an increase in the manufacturing costs or the occurrence of a substrate accumulation effect unlike in the case of using a SOI substrate.
Further, in case of still another semiconductor device according to the present invention, there is provided an insulated gate structure constituted of an electrode formed in a semiconductor substrate and an insulation film formed in the interface between this electrode and the semiconductor substrate; and thus, the above-mentioned electrode can be used as a back gate electrode. Therefore, by applying a suitable voltage to the electrode, the spread of the depletion layer in the channel region of the field-effect transistor can be suppressed, so that, even if the structural minuteness of the elements is furthered, the short channel effect can be suppressed.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.